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00070 #define BOARD_NAME_STKM16 "stkm16"
00071
00072 #ifndef BOARD_STK_M16_H
00073 #define BOARD_STK_M16_H (1)
00074
00075 #define BOARD_TYPE (STK500_MEGA16)
00076 #define BOARD_NAME BOARD_NAME_STKM16
00077
00078
00079 #ifndef MAX_FRAME_SIZE
00080 # define MAX_FRAME_SIZE (127)
00081 #endif
00082
00083 #ifndef DEFAULT_SPI_RATE
00084 # define DEFAULT_SPI_RATE (SPI_RATE_1_2)
00085
00086 #endif
00087
00088
00089 #define CPU_TYPE (CPU_M16)
00090 #define RADIO_TYPE (RADIO_AT86RF230)
00091
00092
00093
00094 #define DDR_TRX_RESET DDRB
00095 #define PORT_TRX_RESET PORTB
00096 #define MASK_TRX_RESET (_BV(PB3))
00097 #define TRX_RESET_INIT() DDR_TRX_RESET |= MASK_TRX_RESET
00098 #define TRX_RESET_HIGH() PORT_TRX_RESET |= MASK_TRX_RESET
00099 #define TRX_RESET_LOW() PORT_TRX_RESET &= ~MASK_TRX_RESET
00100
00101 #define PORT_TRX_SLPTR PORTB
00102 #define DDR_TRX_SLPTR DDRB
00103 #define MASK_TRX_SLPTR (_BV(PB0))
00104
00105 #define TRX_SLPTR_INIT() DDR_TRX_SLPTR |= MASK_TRX_SLPTR
00106 #define TRX_SLPTR_HIGH() PORT_TRX_SLPTR |= MASK_TRX_SLPTR
00107 #define TRX_SLPTR_LOW() PORT_TRX_SLPTR &= ~MASK_TRX_SLPTR
00108
00109
00110
00111 #if 1
00112 # define TRX_IRQ _BV(INT2)
00113 # define TRX_IRQ_vect INT2_vect
00114 # define TRX_IRQ_INIT() do{\
00115 MCUCSR |= _BV(ISC2);\
00116 } while(0)
00117 #else
00118 # define TRX_IRQ _BV(INT0)
00119 # define TRX_IRQ_vect INT0_vect
00120 # define TRX_IRQ_INIT() do{\
00121 MCUCR |= _BV(ISC01) | _BV(ISC00);\
00122 } while(0)
00123 #endif
00124
00125 #define DI_TRX_IRQ() {GICR &= (~(TRX_IRQ));}
00126 #define EI_TRX_IRQ() {GICR |= (TRX_IRQ);}
00127
00129 #define TRX_TSTAMP_REG TCNT1
00130
00131
00132 #define DDR_SPI (DDRB)
00133 #define PORT_SPI (PORTB)
00134
00135 #define SPI_MOSI _BV(PB5)
00136 #define SPI_MISO _BV(PB6)
00137 #define SPI_SCK _BV(PB7)
00138 #define SPI_SS _BV(PB4)
00139
00140 #define SPI_DATA_REG SPDR
00141
00142
00143
00144 static inline void SPI_INIT(uint8_t spirate)
00145 {
00146
00147 PORT_SPI |= SPI_SCK | SPI_SS;
00148 DDR_SPI |= SPI_MOSI | SPI_SCK | SPI_SS;
00149 DDR_SPI &= ~SPI_MISO;
00150
00151 SPCR = (_BV(SPE) | _BV(MSTR));
00152
00153 SPCR &= ~(_BV(SPR1) | _BV(SPR0) );
00154 SPSR &= ~_BV(SPI2X);
00155
00156 SPCR |= (spirate & 0x03);
00157 SPSR |= ((spirate >> 2) & 0x01);
00158
00159 }
00160
00161 #define SPI_SELN_LOW() uint8_t sreg = SREG; cli(); PORT_SPI &=~SPI_SS
00162 #define SPI_SELN_HIGH() PORT_SPI |= SPI_SS; SREG = sreg
00163 #define SPI_WAITFOR() do { while((SPSR & _BV(SPIF)) == 0);} while(0)
00164
00165
00166 #define LED_PORT PORTA
00167 #define LED_DDR DDRA
00168 #define LED_MASK (0xf0)
00169 #define LED_SHIFT (4)
00170 #define LEDS_INVERSE (1)
00171
00172
00173 #define PORT_KEY PORTA
00174 #define PIN_KEY PINA
00175 #define DDR_KEY DDRA
00176 #define MASK_KEY (0x0f)
00177 #define SHIFT_KEY (0x00)
00178 #define INVERSE_KEYS (0)
00179 #define LED_NUMBER (4)
00180
00181 #define HIF_TYPE HIF_UART_0
00182
00183
00184 #define HWTMR_PRESCALE (8)
00185 #define HWTIMER_TICK ((1.0*HWTMR_PRESCALE)/F_CPU)
00186 #define HWTIMER_TICK_NB (1000UL)
00187 #define HWTIMER_REG (TCNT1)
00188 #define TIMER_TICK (HWTIMER_TICK_NB * HWTIMER_TICK)
00189 # define TIMER_POOL_SIZE (4)
00190
00191
00192
00193
00194
00195 # define TIMER_INIT() \
00196 do{ \
00197 TCCR1B |= (_BV(CS11) | _BV(WGM12)); \
00198 TIMSK |= _BV(OCIE1A); \
00199 OCR1A = 1000; \
00200 }while(0)
00201
00202 # define TIMER_IRQ_vect TIMER1_COMPA_vect
00203
00204
00205
00206 #ifndef TUNED_OSCCAL
00207 # define TUNED_OSCCAL (0xbf)
00208 #endif
00209 #endif