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00037 #ifndef AT86RF231_H
00038 #define AT86RF231_H (1)
00039
00040
00041
00042
00043
00044
00045
00046 typedef uint8_t trx_ramaddr_t;
00047 typedef uint8_t trx_regval_t;
00048 typedef uint8_t trx_regaddr_t;
00049
00050
00052 #define RG_TRX_STATUS (0x1)
00053
00054 #define SR_CCA_DONE 0x1,0x80,7
00055
00056 #define SR_CCA_STATUS 0x1,0x40,6
00057
00058 #define SR_TRX_STATUS 0x1,0x1f,0
00059 #define P_ON (0)
00060 #define BUSY_RX (1)
00061 #define BUSY_TX (2)
00062 #define RX_ON (6)
00063 #define TRX_OFF (8)
00064 #define PLL_ON (9)
00065 #define SLEEP (15)
00066 #define BUSY_RX_AACK (17)
00067 #define BUSY_TX_ARET (18)
00068 #define RX_AACK_ON (22)
00069 #define TX_ARET_ON (25)
00070 #define RX_ON_NOCLK (28)
00071 #define RX_AACK_ON_NOCLK (29)
00072 #define BUSY_RX_AACK_NOCLK (30)
00073
00074 #define RG_TRX_STATE (0x2)
00075
00076 #define SR_TRAC_STATUS 0x2,0xe0,5
00077 #define TRAC_SUCCESS (0)
00078 #define TRAC_SUCCESS_DATA_PENDING (1)
00079 #define TRAC_SUCCESS_WAIT_FOR_ACK (2)
00080 #define TRAC_CHANNEL_ACCESS_FAILURE (3)
00081 #define TRAC_NO_ACK (5)
00082 #define TRAC_INVALID (7)
00083
00084 #define SR_TRX_CMD 0x2,0x1f,0
00085 #define CMD_NOP (0)
00086 #define CMD_TX_START (2)
00087 #define CMD_FORCE_TRX_OFF (3)
00088 #define CMD_RX_ON (6)
00089 #define CMD_TRX_OFF (8)
00090 #define CMD_PLL_ON (9)
00091 #define CMD_RX_AACK_ON (22)
00092 #define CMD_TX_ARET_ON (25)
00093
00094 #define RG_TRX_CTRL_0 (0x3)
00095
00096 #define SR_PAD_IO 0x3,0xe0,5
00097
00098 #define SR_PAD_IO_CLKM 0x3,0x10,4
00099 #define CLKM_2mA (0)
00100 #define CLKM_4mA (1)
00101 #define CLKM_6mA (2)
00102 #define CLKM_8mA (3)
00103
00104 #define SR_CLKM_SHA_SEL 0x3,0x8,3
00105
00106 #define SR_CLKM_CTRL 0x3,0x7,0
00107 #define CLKM_no_clock (0)
00108 #define CLKM_1MHz (1)
00109 #define CLKM_2MHz (2)
00110 #define CLKM_4MHz (3)
00111 #define CLKM_8MHz (4)
00112 #define CLKM_16MHz (5)
00113
00114 #define RG_TRX_CTRL_1 (0x4)
00115
00116 #define SR_PA_EXT_EN 0x4,0x80,7
00117
00118 #define SR_IRQ_2_EXT_EN 0x4,0x40,6
00119
00120 #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
00121
00122 #define SR_RX_BL_CTRL 0x4,0x10,4
00123
00124 #define SR_SPI_CMD_MODE 0x4,0xc,2
00125
00126 #define SR_IRQ_MASK_MODE 0x4,0x3,0
00127
00128 #define RG_PHY_TX_PWR (0x5)
00129
00130 #define SR_PA_BUF_LT 0x5,0xc0,6
00131
00132 #define SR_PA_LT 0x5,0x30,4
00133
00134 #define SR_TX_PWR 0x5,0xf,0
00135
00136 #define RG_PHY_RSSI (0x6)
00137
00138 #define SR_RX_CRC_VALID 0x6,0x80,7
00139
00140 #define SR_RND_VALUE 0x6,0x60,5
00141
00142 #define SR_RSSI 0x6,0x1f,0
00143
00144 #define RG_PHY_ED_LEVEL (0x7)
00145
00146 #define SR_ED_LEVEL 0x7,0xff,0
00147
00148 #define RG_PHY_CC_CCA (0x8)
00149
00150 #define SR_CCA_REQUEST 0x8,0x80,7
00151
00152 #define SR_CCA_MODE 0x8,0x60,5
00153
00154 #define SR_CHANNEL 0x8,0x1f,0
00155
00156 #define RG_CCA_THRES (0x9)
00157
00158 #define SR_CCA_ED_THRES 0x9,0xf,0
00159
00160 #define RG_RX_CTRL (0xa)
00161
00162 #define SR_PDT_THRES 0xa,0xf,0
00163
00164 #define RG_SFD_VALUE (0xb)
00165
00166 #define SR_SFD_VALUE 0xb,0xff,0
00167
00168 #define RG_TRX_CTRL_2 (0xc)
00169
00170 #define SR_RX_SAFE_MODE 0xc,0x80,7
00171
00172 #define SR_OQPSK_DATA_RATE 0xc,0x3,0
00173
00174 #define RG_ANT_DIV (0xd)
00175
00176 #define SR_ANT_SEL 0xd,0x80,7
00177
00178 #define SR_ANT_DIV_EN 0xd,0x8,3
00179
00180 #define SR_ANT_EXT_SW_EN 0xd,0x4,2
00181
00182 #define SR_ANT_CTRL 0xd,0x3,0
00183
00184 #define RG_IRQ_MASK (0xe)
00185
00186 #define SR_MASK_BAT_LOW 0xe,0x80,7
00187
00188 #define SR_MASK_TRX_UR 0xe,0x40,6
00189
00190 #define SR_MASK_AMI 0xe,0x20,5
00191
00192 #define SR_MASK_CCA_ED_READY 0xe,0x10,4
00193
00194 #define SR_MASK_TRX_END 0xe,0x8,3
00195
00196 #define SR_MASK_TRX_START 0xe,0x4,2
00197
00198 #define SR_MASK_PLL_UNLOCK 0xe,0x3,0
00199
00200 #define RG_IRQ_STATUS (0xf)
00201
00202 #define SR_BAT_LOW 0xf,0x80,7
00203
00204 #define SR_TRX_UR 0xf,0x40,6
00205
00206 #define SR_AMI 0xf,0x20,5
00207
00208 #define SR_CCA_ED_READY 0xf,0x10,4
00209
00210 #define SR_RX_END 0xf,0x8,3
00211
00212 #define SR_RX_START 0xf,0x4,2
00213
00214 #define SR_PLL_UNLOCK 0xf,0x3,0
00215
00216 #define RG_VREG_CTRL (0x10)
00217
00218 #define SR_AVREG_EXT 0x10,0x80,7
00219
00220 #define SR_AVDD_OK 0x10,0x40,6
00221
00222 #define SR_DVREG_EXT 0x10,0x8,3
00223
00224 #define SR_DVDD_OK 0x10,0x4,2
00225
00226 #define RG_BATMON (0x11)
00227
00228 #define SR_BATMON_OK 0x11,0x20,5
00229
00230 #define SR_BATMON_HR 0x11,0x10,4
00231
00232 #define SR_BATMON_VTH 0x11,0xf,0
00233
00234 #define RG_XOSC_CTRL (0x12)
00235
00236 #define SR_XTAL_MODE 0x12,0xf0,4
00237
00238 #define SR_XTAL_TRIM 0x12,0xf,0
00239
00240 #define RG_RX_SYN (0x15)
00241
00242 #define SR_RX_PDT_DIS 0x15,0x80,7
00243
00244 #define SR_RX_PDT_LEVEL 0x15,0xf,0
00245
00246 #define RG_XAH_CTRL_1 (0x17)
00247
00248 #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
00249
00250 #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
00251
00252 #define SR_AACK_ACK_TIME 0x17,0x4,2
00253
00254 #define SR_AACK_PROM_MODE 0x17,0x3,0
00255
00256 #define RG_FTN_CTRL (0x18)
00257
00258 #define SR_FTN_START 0x18,0x80,7
00259
00260 #define RG_PLL_CF (0x1a)
00261
00262 #define SR_PLL_CF_START 0x1a,0x80,7
00263
00264 #define RG_PLL_DCU (0x1b)
00265
00266 #define SR_PLL_DCU_START 0x1b,0x80,7
00267
00268 #define RG_PART_NUM (0x1c)
00269
00270 #define SR_PART_NUM 0x1c,0xff,0
00271 #define RF231A_PART_NUM (3)
00272
00273 #define RG_VERSION_NUM (0x1d)
00274
00275 #define SR_VERSION_NUM 0x1d,0xff,0
00276 #define RF231A_VERSION_NUM (2)
00277
00278 #define RG_MAN_ID_0 (0x1e)
00279
00280 #define SR_MAN_ID_0 0x1e,0xff,0
00281
00282 #define RG_MAN_ID_1 (0x1f)
00283
00284 #define SR_MAN_ID_1 0x1f,0xff,0
00285
00286 #define RG_SHORT_ADDR_0 (0x20)
00287
00288 #define SR_SHORT_ADDR_0 0x20,0xff,0
00289
00290 #define RG_SHORT_ADDR_1 (0x21)
00291
00292 #define SR_SHORT_ADDR_1 0x21,0xff,0
00293
00294 #define RG_PAN_ID_0 (0x22)
00295
00296 #define SR_PAN_ID_0 0x22,0xff,0
00297
00298 #define RG_PAN_ID_1 (0x23)
00299
00300 #define SR_PAN_ID_1 0x23,0xff,0
00301
00302 #define RG_IEEE_ADDR_0 (0x24)
00303
00304 #define SR_IEEE_ADDR_0 0x24,0xff,0
00305
00306 #define RG_IEEE_ADDR_1 (0x25)
00307
00308 #define SR_IEEE_ADDR_1 0x25,0xff,0
00309
00310 #define RG_IEEE_ADDR_2 (0x26)
00311
00312 #define SR_IEEE_ADDR_2 0x26,0xff,0
00313
00314 #define RG_IEEE_ADDR_3 (0x27)
00315
00316 #define SR_IEEE_ADDR_3 0x27,0xff,0
00317
00318 #define RG_IEEE_ADDR_4 (0x28)
00319
00320 #define SR_IEEE_ADDR_4 0x28,0xff,0
00321
00322 #define RG_IEEE_ADDR_5 (0x29)
00323
00324 #define SR_IEEE_ADDR_5 0x29,0xff,0
00325
00326 #define RG_IEEE_ADDR_6 (0x2a)
00327
00328 #define SR_IEEE_ADDR_6 0x2a,0xff,0
00329
00330 #define RG_IEEE_ADDR_7 (0x2b)
00331
00332 #define SR_IEEE_ADDR_7 0x2b,0xff,0
00333
00334 #define RG_XAH_CTRL_0 (0x2c)
00335
00336 #define SR_MAX_FRAME_RETRES 0x2c,0xf0,4
00337
00338 #define SR_MAX_CSMA_RETRES 0x2c,0xf,0
00339
00340 #define RG_CSMA_SEED_0 (0x2d)
00341
00342 #define SR_CSMA_SEED_0 0x2d,0xff,0
00343
00344 #define RG_CSMA_SEED_1 (0x2e)
00345
00346 #define SR_AACK_FVN_MODE 0x2e,0xc0,6
00347
00348 #define SR_AACK_SET_PD 0x2e,0x20,5
00349
00350 #define SR_AACK_DIS_ACK 0x2e,0x10,4
00351
00352 #define SR_AACK_I_AM_COORD 0x2e,0x8,3
00353
00354 #define SR_CSMA_SEED_1 0x2e,0x7,0
00355
00356 #define RG_CSMA_BE (0x2f)
00357
00358 #define SR_MAX_BE 0x2f,0xf0,4
00359
00360 #define SR_MIN_BE 0x2f,0xf,0
00361
00362 #define RADIO_NAME "AT86RF231"
00363
00364 #define RADIO_PART_NUM (RF231A_PART_NUM)
00365
00366 #define RADIO_VERSION_NUM (RF231A_VERSION_NUM)
00367
00369 #define TRX_CMD_RW (_BV(7) | _BV(6))
00370
00371 #define TRX_CMD_RR (_BV(7))
00372
00373 #define TRX_CMD_FW (_BV(6) | _BV(5))
00374
00375 #define TRX_CMD_FR (_BV(5))
00376
00377 #define TRX_CMD_SW (_BV(6))
00378
00379 #define TRX_CMD_SR (0)
00380
00381 #define TRX_CMD_RADDR_MASK (0x3f)
00382
00384 #define TRX_RESET_TIME_US (6)
00385
00387 #define TRX_INIT_TIME_US (510)
00388
00390 #define TRX_PLL_LOCK_TIME_US (180)
00391
00392
00394 #define TRX_CCA_TIME_US (140)
00395
00397 #define TRX_IRQ_PLL_LOCK _BV(0)
00398
00400 #define TRX_IRQ_PLL_UNLOCK _BV(1)
00401
00403 #define TRX_IRQ_RX_START _BV(2)
00404
00406 #define TRX_IRQ_TRX_END _BV(3)
00407
00409 #define TRX_IRQ_CCA_ED _BV(4)
00410
00412 #define TRX_IRQ_AMI _BV(5)
00413
00415 #define TRX_IRQ_UR _BV(6)
00416
00418 #define TRX_IRQ_BAT_LOW _BV(7)
00419
00421 #define TRAC_SUCCESS (0)
00422
00423 #define TRAC_CHANNEL_ACCESS_FAILURE (3)
00424
00425 #define TRAC_NO_ACK (5)
00426
00427
00429 #define TRX_MIN_CHANNEL (11)
00430
00432 #define TRX_MAX_CHANNEL (26)
00433
00435 #define TRX_NB_CHANNELS (16)
00436
00441 #define TRX_SUPPORTED_CHANNELS (0x7fff800UL)
00442
00443 #define TRX_SUPPORTS_BAND_2400 (1)
00444
00448 #define TRX_SUPPORTED_PAGES (42)
00449
00451 #define RATE_CODE_OQPSK250 (0)
00452
00454 #define RATE_CODE_OQPSK500 (1)
00455
00457 #define RATE_CODE_OQPSK1000 (2)
00458
00459 #define RATE_CODE_OQPSK2000 (3)
00460
00461 #define RATE_CODE_NONE (255)
00462
00463 #endif