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00037 #ifndef AT86RF230A_H
00038 #define AT86RF230A_H (1)
00039
00040
00041
00042
00043
00044
00045
00046 typedef uint8_t trx_ramaddr_t;
00047 typedef uint8_t trx_regval_t;
00048 typedef uint8_t trx_regaddr_t;
00049
00050
00052 #define RG_TRX_STATUS (0x1)
00053
00054 #define SR_CCA_DONE 0x1,0x80,7
00055
00056 #define SR_CCA_STATUS 0x1,0x40,6
00057
00058 #define SR_TRX_STATUS 0x1,0x1f,0
00059 #define P_ON (0)
00060 #define BUSY_RX (1)
00061 #define BUSY_TX (2)
00062 #define RX_ON (6)
00063 #define TRX_OFF (8)
00064 #define PLL_ON (9)
00065 #define SLEEP (15)
00066 #define BUSY_RX_AACK (17)
00067 #define BUSY_TX_ARET (18)
00068 #define RX_AACK_ON (22)
00069 #define TX_ARET_ON (25)
00070 #define RX_ON_NOCLK (28)
00071 #define RX_AACK_ON_NOCLK (29)
00072 #define BUSY_RX_AACK_NOCLK (30)
00073
00074 #define RG_TRX_STATE (0x2)
00075
00076 #define SR_TRAC_STATUS 0x2,0xe0,5
00077 #define TRAC_SUCCESS (0)
00078 #define TRAC_CHANNEL_ACCESS_FAILURE (3)
00079 #define TRAC_NO_ACK (5)
00080
00081 #define SR_TRX_CMD 0x2,0x1f,0
00082 #define CMD_NOP (0)
00083 #define CMD_TX_START (2)
00084 #define CMD_FORCE_TRX_OFF (3)
00085 #define CMD_RX_ON (6)
00086 #define CMD_TRX_OFF (8)
00087 #define CMD_PLL_ON (9)
00088 #define CMD_RX_AACK_ON (22)
00089 #define CMD_TX_ARET_ON (25)
00090
00091 #define RG_TRX_CTRL_0 (0x3)
00092
00093 #define SR_PAD_IO 0x3,0xc0,6
00094
00095 #define SR_PAD_IO_CLKM 0x3,0x30,4
00096 #define CLKM_2mA (0)
00097 #define CLKM_4mA (1)
00098 #define CLKM_6mA (2)
00099 #define CLKM_8mA (3)
00100
00101 #define SR_CLKM_SHA_SEL 0x3,0x8,3
00102
00103 #define SR_CLKM_CTRL 0x3,0x7,0
00104 #define CLKM_no_clock (0)
00105 #define CLKM_1MHz (1)
00106 #define CLKM_2MHz (2)
00107 #define CLKM_4MHz (3)
00108 #define CLKM_8MHz (4)
00109 #define CLKM_16MHz (5)
00110
00111 #define RG_PHY_TX_PWR (0x5)
00112
00113 #define SR_TX_AUTO_CRC_ON 0x5,0x80,7
00114
00115 #define SR_TX_PWR 0x5,0xf,0
00116
00117 #define RG_PHY_RSSI (0x6)
00118
00119 #define SR_RSSI 0x6,0x1f,0
00120
00121 #define RG_PHY_ED_LEVEL (0x7)
00122
00123 #define SR_ED_LEVEL 0x7,0xff,0
00124
00125 #define RG_PHY_CC_CCA (0x8)
00126
00127 #define SR_CCA_REQUEST 0x8,0x80,7
00128
00129 #define SR_CCA_MODE 0x8,0x60,5
00130
00131 #define SR_CHANNEL 0x8,0x1f,0
00132
00133 #define RG_CCA_THRES (0x9)
00134
00135 #define SR_CCA_ED_THRES 0x9,0xf,0
00136
00137 #define RG_IRQ_MASK (0xe)
00138
00139 #define SR_MASK_BAT_LOW 0xe,0x80,7
00140
00141 #define SR_MASK_TRX_UR 0xe,0x40,6
00142
00143 #define SR_MASK_TRX_END 0xe,0x8,3
00144
00145 #define SR_MASK_TRX_START 0xe,0x4,2
00146
00147 #define SR_MASK_PLL_UNLOCK 0xe,0x3,0
00148
00149 #define RG_IRQ_STATUS (0xf)
00150
00151 #define SR_BAT_LOW 0xf,0x80,7
00152
00153 #define SR_TRX_UR 0xf,0x40,6
00154
00155 #define SR_RX_END 0xf,0x8,3
00156
00157 #define SR_RX_START 0xf,0x4,2
00158
00159 #define SR_PLL_UNLOCK 0xf,0x3,0
00160
00161 #define RG_VREG_CTRL (0x10)
00162
00163 #define SR_AVREG_EXT 0x10,0x80,7
00164
00165 #define SR_AVDD_OK 0x10,0x40,6
00166
00167 #define SR_DVREG_EXT 0x10,0x8,3
00168
00169 #define SR_DVDD_OK 0x10,0x4,2
00170
00171 #define RG_BATMON (0x11)
00172
00173 #define SR_BATMON_OK 0x11,0x20,5
00174
00175 #define SR_BATMON_HR 0x11,0x10,4
00176
00177 #define SR_BATMON_VTH 0x11,0xf,0
00178
00179 #define RG_XOSC_CTRL (0x12)
00180
00181 #define SR_XTAL_MODE 0x12,0xf0,4
00182
00183 #define SR_XTAL_TRIM 0x12,0xf,0
00184
00185 #define RG_PLL_CF (0x1a)
00186
00187 #define SR_PLL_CF_START 0x1a,0x80,7
00188
00189 #define RG_PLL_DCU (0x1b)
00190
00191 #define SR_PLL_DCU_START 0x1b,0x80,7
00192
00193 #define RG_PART_NUM (0x1c)
00194
00195 #define SR_PART_NUM 0x1c,0xff,0
00196 #define RF230A_PART_NUM (2)
00197
00198 #define RG_VERSION_NUM (0x1d)
00199
00200 #define SR_VERSION_NUM 0x1d,0xff,0
00201 #define RF230A_VERSION_NUM (1)
00202
00203 #define RG_MAN_ID_0 (0x1e)
00204
00205 #define SR_MAN_ID_0 0x1e,0xff,0
00206
00207 #define RG_MAN_ID_1 (0x1f)
00208
00209 #define SR_MAN_ID_1 0x1f,0xff,0
00210
00211 #define RG_SHORT_ADDR_0 (0x20)
00212
00213 #define SR_SHORT_ADDR_0 0x20,0xff,0
00214
00215 #define RG_SHORT_ADDR_1 (0x21)
00216
00217 #define SR_SHORT_ADDR_1 0x21,0xff,0
00218
00219 #define RG_PAN_ID_0 (0x22)
00220
00221 #define SR_PAN_ID_0 0x22,0xff,0
00222
00223 #define RG_PAN_ID_1 (0x23)
00224
00225 #define SR_PAN_ID_1 0x23,0xff,0
00226
00227 #define RG_IEEE_ADDR_0 (0x24)
00228
00229 #define SR_IEEE_ADDR_0 0x24,0xff,0
00230
00231 #define RG_IEEE_ADDR_1 (0x25)
00232
00233 #define SR_IEEE_ADDR_1 0x25,0xff,0
00234
00235 #define RG_IEEE_ADDR_2 (0x26)
00236
00237 #define SR_IEEE_ADDR_2 0x26,0xff,0
00238
00239 #define RG_IEEE_ADDR_3 (0x27)
00240
00241 #define SR_IEEE_ADDR_3 0x27,0xff,0
00242
00243 #define RG_IEEE_ADDR_4 (0x28)
00244
00245 #define SR_IEEE_ADDR_4 0x28,0xff,0
00246
00247 #define RG_IEEE_ADDR_5 (0x29)
00248
00249 #define SR_IEEE_ADDR_5 0x29,0xff,0
00250
00251 #define RG_IEEE_ADDR_6 (0x2a)
00252
00253 #define SR_IEEE_ADDR_6 0x2a,0xff,0
00254
00255 #define RG_IEEE_ADDR_7 (0x2b)
00256
00257 #define SR_IEEE_ADDR_7 0x2b,0xff,0
00258
00259 #define RG_XAH_CTRL (0x2c)
00260
00261 #define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4
00262
00263 #define SR_MAX_CSMA_RETRIES 0x2c,0xf,0
00264
00265 #define RG_CSMA_SEED_0 (0x2d)
00266
00267 #define SR_CSMA_SEED_0 0x2d,0xff,0
00268
00269 #define RG_CSMA_SEED_1 (0x2e)
00270
00271 #define SR_MIN_BE 0x2e,0xc0,6
00272
00273 #define SR_AACK_I_AM_COORD 0x2e,0x8,3
00274
00275 #define SR_CSMA_SEED_1 0x2e,0x7,0
00276
00277 #define RADIO_NAME "AT86RF230A"
00278
00279 #define RADIO_PART_NUM (RF230A_PART_NUM)
00280
00281 #define RADIO_VERSION_NUM (RF230A_VERSION_NUM)
00282
00283
00285 #define TRX_CMD_RW (_BV(7) | _BV(6))
00286
00287 #define TRX_CMD_RR (_BV(7))
00288
00289 #define TRX_CMD_FW (_BV(6) | _BV(5))
00290
00291 #define TRX_CMD_FR (_BV(5))
00292
00293 #define TRX_CMD_SW (_BV(6))
00294
00295 #define TRX_CMD_SR (0)
00296
00297 #define TRX_CMD_RADDR_MASK (0x3f)
00298
00300 #define TRX_RESET_TIME_US (6)
00301
00303 #define TRX_INIT_TIME_US (510)
00304
00306 #define TRX_PLL_LOCK_TIME_US (180)
00307
00309 #define TRX_CCA_TIME_US (140)
00310
00312 #define TRX_IRQ_PLL_LOCK _BV(0)
00313
00315 #define TRX_IRQ_PLL_UNLOCK _BV(1)
00316
00318 #define TRX_IRQ_RX_START _BV(2)
00319
00321 #define TRX_IRQ_TRX_END _BV(3)
00322
00324 #define TRX_IRQ_UR _BV(6)
00325
00327 #define TRX_IRQ_BAT_LOW _BV(7)
00328
00330 #define TRX_MIN_CHANNEL (11)
00331
00333 #define TRX_MAX_CHANNEL (26)
00334
00336 #define TRX_NB_CHANNELS (16)
00337
00342 #define TRX_SUPPORTED_CHANNELS (0x7fff800UL)
00343
00347 #define TRX_SUPPORTED_MODULATIONS (MODULATION_OQPSK_250)
00348
00353 #define TRX_SUPPORTED_PAGES (42)
00354
00355 #define TRX_SUPPORTS_BAND_2400 (1)
00356
00358 #define RATE_CODE_OQPSK250 (0)
00359
00361 #define RATE_CODE_NONE (255)
00362
00363 #endif