at86rf230b.h

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00001 /* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf230b.txt */
00002 
00003 /* Copyright (c) 2008 Axel Wachtler
00004    All rights reserved.
00005 
00006    Redistribution and use in source and binary forms, with or without
00007    modification, are permitted provided that the following conditions
00008    are met:
00009 
00010    * Redistributions of source code must retain the above copyright
00011      notice, this list of conditions and the following disclaimer.
00012    * Redistributions in binary form must reproduce the above copyright
00013      notice, this list of conditions and the following disclaimer in the
00014      documentation and/or other materials provided with the distribution.
00015    * Neither the name of the authors nor the names of its contributors
00016      may be used to endorse or promote products derived from this software
00017      without specific prior written permission.
00018 
00019    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00020    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00021    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00022    ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
00023    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00024    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00025    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00026    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00027    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00028    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00029    POSSIBILITY OF SUCH DAMAGE. */
00030 
00031 /* $Id: at86rf230b_8h_source.html,v 1.1.1.4 2013/04/09 21:11:49 awachtler Exp $ */
00036 #ifndef AT86RF230B_H
00037 #define AT86RF230B_H (1)
00038 
00039 /* === Includes ============================================================== */
00040 
00041 /* === Externals ============================================================= */
00042 
00043 /* === Types ================================================================= */
00044 
00045 typedef uint8_t trx_ramaddr_t;
00046 typedef uint8_t trx_regval_t;
00047 typedef uint8_t trx_regaddr_t;
00048 
00049 /* === Macros ================================================================ */
00051 #define RG_TRX_STATUS (0x1)
00052 
00053   #define SR_CCA_DONE 0x1,0x80,7
00054 
00055   #define SR_CCA_STATUS 0x1,0x40,6
00056 
00057   #define SR_TRX_STATUS 0x1,0x1f,0
00058     #define P_ON (0)
00059     #define BUSY_RX (1)
00060     #define BUSY_TX (2)
00061     #define RX_ON (6)
00062     #define TRX_OFF (8)
00063     #define PLL_ON (9)
00064     #define TRX_SLEEP (15)
00065     #define BUSY_RX_AACK (17)
00066     #define BUSY_TX_ARET (18)
00067     #define RX_AACK_ON (22)
00068     #define TX_ARET_ON (25)
00069     #define RX_ON_NOCLK (28)
00070     #define RX_AACK_ON_NOCLK (29)
00071     #define BUSY_RX_AACK_NOCLK (30)
00072 
00073 #define RG_TRX_STATE (0x2)
00074 
00075   #define SR_TRAC_STATUS 0x2,0xe0,5
00076     #define TRAC_SUCCESS (0)
00077     #define TRAC_SUCCESS_DATA_PENDING (1)
00078     #define TRAC_CHANNEL_ACCESS_FAILURE (3)
00079     #define TRAC_NO_ACK (5)
00080     #define TRAC_INVALID (7)
00081 
00082   #define SR_TRX_CMD 0x2,0x1f,0
00083     #define CMD_NOP (0)
00084     #define CMD_TX_START (2)
00085     #define CMD_FORCE_TRX_OFF (3)
00086     #define CMD_RX_ON (6)
00087     #define CMD_TRX_OFF (8)
00088     #define CMD_PLL_ON (9)
00089     #define CMD_RX_AACK_ON (22)
00090     #define CMD_TX_ARET_ON (25)
00091 
00092 #define RG_TRX_CTRL_0 (0x3)
00093 
00094   #define SR_PAD_IO 0x3,0xc0,6
00095 
00096   #define SR_PAD_IO_CLKM 0x3,0x30,4
00097     #define CLKM_2mA (0)
00098     #define CLKM_4mA (1)
00099     #define CLKM_6mA (2)
00100     #define CLKM_8mA (3)
00101 
00102   #define SR_CLKM_SHA_SEL 0x3,0x8,3
00103 
00104   #define SR_CLKM_CTRL 0x3,0x7,0
00105     #define CLKM_no_clock (0)
00106     #define CLKM_1MHz (1)
00107     #define CLKM_2MHz (2)
00108     #define CLKM_4MHz (3)
00109     #define CLKM_8MHz (4)
00110     #define CLKM_16MHz (5)
00111 
00112 #define RG_PHY_TX_PWR (0x5)
00113 
00114   #define SR_TX_AUTO_CRC_ON 0x5,0x80,7
00115 
00116   #define SR_TX_PWR 0x5,0xf,0
00117 
00118 #define RG_PHY_RSSI (0x6)
00119 
00120   #define SR_RX_CRC_VALID 0x6,0x80,7
00121 
00122   #define SR_RSSI 0x6,0x1f,0
00123 
00124 #define RG_PHY_ED_LEVEL (0x7)
00125 
00126   #define SR_ED_LEVEL 0x7,0xff,0
00127 
00128 #define RG_PHY_CC_CCA (0x8)
00129 
00130   #define SR_CCA_REQUEST 0x8,0x80,7
00131 
00132   #define SR_CCA_MODE 0x8,0x60,5
00133 
00134   #define SR_CHANNEL 0x8,0x1f,0
00135 
00136 #define RG_CCA_THRES (0x9)
00137 
00138   #define SR_CCA_ED_THRES 0x9,0xf,0
00139 
00140 #define RG_IRQ_MASK (0xe)
00141 
00142   #define SR_MASK_BAT_LOW 0xe,0x80,7
00143 
00144   #define SR_MASK_TRX_UR 0xe,0x40,6
00145 
00146   #define SR_MASK_TRX_END 0xe,0x8,3
00147 
00148   #define SR_MASK_TRX_START 0xe,0x4,2
00149 
00150   #define SR_MASK_PLL_LOCK 0xe,0x1,0
00151 
00152   #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
00153 
00154 #define RG_IRQ_STATUS (0xf)
00155 
00156   #define SR_BAT_LOW 0xf,0x80,7
00157 
00158   #define SR_TRX_UR 0xf,0x40,6
00159 
00160   #define SR_RX_END 0xf,0x8,3
00161 
00162   #define SR_RX_START 0xf,0x4,2
00163 
00164   #define SR_PLL_LOCK 0xf,0x1,0
00165 
00166   #define SR_PLL_UNLOCK 0xf,0x2,1
00167 
00168 #define RG_VREG_CTRL (0x10)
00169 
00170   #define SR_AVREG_EXT 0x10,0x80,7
00171 
00172   #define SR_AVDD_OK 0x10,0x40,6
00173 
00174   #define SR_DVREG_EXT 0x10,0x8,3
00175 
00176   #define SR_DVDD_OK 0x10,0x4,2
00177 
00178 #define RG_BATMON (0x11)
00179 
00180   #define SR_BATMON_OK 0x11,0x20,5
00181 
00182   #define SR_BATMON_HR 0x11,0x10,4
00183 
00184   #define SR_BATMON_VTH 0x11,0xf,0
00185 
00186 #define RG_XOSC_CTRL (0x12)
00187 
00188   #define SR_XTAL_MODE 0x12,0xf0,4
00189 
00190   #define SR_XTAL_TRIM 0x12,0xf,0
00191 
00192 #define RG_PLL_CF (0x1a)
00193 
00194   #define SR_PLL_CF_START 0x1a,0x80,7
00195 
00196 #define RG_PLL_DCU (0x1b)
00197 
00198   #define SR_PLL_DCU_START 0x1b,0x80,7
00199 
00200 #define RG_PART_NUM (0x1c)
00201 
00202   #define SR_PART_NUM 0x1c,0xff,0
00203     #define RF230B_PART_NUM (2)
00204 
00205 #define RG_VERSION_NUM (0x1d)
00206 
00207   #define SR_VERSION_NUM 0x1d,0xff,0
00208     #define RF230B_VERSION_NUM (2)
00209 
00210 #define RG_MAN_ID_0 (0x1e)
00211 
00212   #define SR_MAN_ID_0 0x1e,0xff,0
00213 
00214 #define RG_MAN_ID_1 (0x1f)
00215 
00216   #define SR_MAN_ID_1 0x1f,0xff,0
00217 
00218 #define RG_SHORT_ADDR_0 (0x20)
00219 
00220   #define SR_SHORT_ADDR_0 0x20,0xff,0
00221 
00222 #define RG_SHORT_ADDR_1 (0x21)
00223 
00224   #define SR_SHORT_ADDR_1 0x21,0xff,0
00225 
00226 #define RG_PAN_ID_0 (0x22)
00227 
00228   #define SR_PAN_ID_0 0x22,0xff,0
00229 
00230 #define RG_PAN_ID_1 (0x23)
00231 
00232   #define SR_PAN_ID_1 0x23,0xff,0
00233 
00234 #define RG_IEEE_ADDR_0 (0x24)
00235 
00236   #define SR_IEEE_ADDR_0 0x24,0xff,0
00237 
00238 #define RG_IEEE_ADDR_1 (0x25)
00239 
00240   #define SR_IEEE_ADDR_1 0x25,0xff,0
00241 
00242 #define RG_IEEE_ADDR_2 (0x26)
00243 
00244   #define SR_IEEE_ADDR_2 0x26,0xff,0
00245 
00246 #define RG_IEEE_ADDR_3 (0x27)
00247 
00248   #define SR_IEEE_ADDR_3 0x27,0xff,0
00249 
00250 #define RG_IEEE_ADDR_4 (0x28)
00251 
00252   #define SR_IEEE_ADDR_4 0x28,0xff,0
00253 
00254 #define RG_IEEE_ADDR_5 (0x29)
00255 
00256   #define SR_IEEE_ADDR_5 0x29,0xff,0
00257 
00258 #define RG_IEEE_ADDR_6 (0x2a)
00259 
00260   #define SR_IEEE_ADDR_6 0x2a,0xff,0
00261 
00262 #define RG_IEEE_ADDR_7 (0x2b)
00263 
00264   #define SR_IEEE_ADDR_7 0x2b,0xff,0
00265 
00266 #define RG_XAH_CTRL (0x2c)
00267 
00268   #define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4
00269 
00270   #define SR_MAX_CSMA_RETRIES 0x2c,0xe,1
00271 
00272 #define RG_CSMA_SEED_0 (0x2d)
00273 
00274   #define SR_CSMA_SEED_0 0x2d,0xff,0
00275 
00276 #define RG_CSMA_SEED_1 (0x2e)
00277 
00278   #define SR_MIN_BE 0x2e,0xc0,6
00279 
00280   #define SR_AACK_SET_PD 0x2e,0x20,5
00281 
00282   #define SR_AACK_I_AM_COORD 0x2e,0x8,3
00283 
00284   #define SR_CSMA_SEED_1 0x2e,0x7,0
00285 
00286 #define RADIO_NAME "AT86RF230B"
00287 
00288 #define RADIO_PART_NUM (RF230B_PART_NUM)
00289 
00290 #define RADIO_VERSION_NUM (RF230B_VERSION_NUM)
00291 
00293 #define TRX_CMD_RW           (_BV(7) | _BV(6))
00294 
00295 #define TRX_CMD_RR           (_BV(7))
00296 
00297 #define TRX_CMD_FW           (_BV(6) | _BV(5))
00298 
00299 #define TRX_CMD_FR           (_BV(5))
00300 
00301 #define TRX_CMD_SW           (_BV(6))
00302 
00303 #define TRX_CMD_SR           (0)
00304 
00305 #define TRX_CMD_RADDR_MASK   (0x3f)
00306 
00308 #define TRX_RESET_TIME_US    (6)
00309 
00311 #define TRX_INIT_TIME_US     (510)
00312 
00314 #define TRX_PLL_LOCK_TIME_US     (180)
00315 
00317 #define TRX_CCA_TIME_US     (140)
00318 
00320 #define TRX_IRQ_PLL_LOCK   _BV(0)
00321 
00323 #define TRX_IRQ_PLL_UNLOCK _BV(1)
00324 
00326 #define TRX_IRQ_RX_START   _BV(2)
00327 
00329 #define TRX_IRQ_TRX_END    _BV(3)
00330 
00332 #define TRX_IRQ_UR         _BV(6)
00333 
00335 #define TRX_IRQ_BAT_LOW    _BV(7)
00336 
00337 
00338 
00340 #define TRX_MIN_CHANNEL (11)
00341 
00343 #define TRX_MAX_CHANNEL (26)
00344 
00346 #define TRX_NB_CHANNELS (16)
00347 
00352 #define TRX_SUPPORTED_CHANNELS  (0x7fff800UL)
00353 
00354 #define TRX_SUPPORTS_BAND_2400 (1)
00355 
00360 #define TRX_SUPPORTED_PAGES     (42)
00361 
00362 
00364 #define TRX_OQPSK250  (0)
00365 
00367 #define TRX_NONE      (255)
00368 
00369 #endif /* ifndef AT86RF230B_H */

This documentation for µracoli was generated on Tue Apr 9 2013 by  doxygen 1.7.1