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00035 #ifndef TRANSCEIVER_H
00036 #define TRANSCEIVER_H
00037
00043
00044 #include "board.h"
00045
00046 #if RADIO_TYPE == RADIO_AT86RF230 || defined(DOXYGEN)
00047 # include "at86rf230a.h"
00048 #elif RADIO_TYPE == RADIO_AT86RF230B
00049 # include "at86rf230b.h"
00050 #elif RADIO_TYPE == RADIO_AT86RF231
00051 # include "at86rf231.h"
00052 #elif RADIO_TYPE == RADIO_AT86RF212
00053 # include "at86rf212.h"
00054 #elif RADIO_TYPE == RADIO_ATMEGA128RFA1_A ||\
00055 RADIO_TYPE == RADIO_ATMEGA128RFA1_B ||\
00056 RADIO_TYPE == RADIO_ATMEGA128RFA1_C ||\
00057 RADIO_TYPE == RADIO_ATMEGA128RFA1_D
00058 # include "atmega_rfa1.h"
00059 #else
00060 # error "RADIO_TYPE is not defined or wrong"
00061 #endif
00062 #include <stdbool.h>
00063
00064
00065
00066
00067
00068 #if defined(DOXYGEN)
00069
00070
00071
00072
00075 typedef uint8_t trx_ramaddr_t;
00076
00079 typedef uint8_t trx_regval_t;
00080
00083 typedef uint8_t trx_regaddr_t;
00084
00085 #endif
00086
00089 typedef void (*trx_irq_handler_t)(uint8_t cause);
00090
00091 typedef enum
00092 {
00093 CFG_FLASH,
00094 CFG_EEPROM,
00095 CFG_NONE
00096 } trx_cfg_t;
00097
00098
00099
00100
00101 #define INVALID_PART_NUM (2)
00102 #define INVALID_REV_NUM (1)
00104
00105 #define BPSK20_HSH (0x52)
00106 #define BPSK20_STR "BPSK20"
00107 #define BPSK40_HSH (0x92)
00108 #define BPSK40_STR "BPSK40"
00109 #define OQPSK100_HSH (0x90)
00110 #define OQPSK100_STR "OQPSK100"
00111 #define OQPSK200_HSH (0x93)
00112 #define OQPSK200_STR "OQPSK200"
00113 #define OQPSK250_HSH (0x33)
00114 #define OQPSK250_STR "OQPSK250"
00115 #define OQPSK400_HSH (0x95)
00116 #define OQPSK400_STR "OQPSK400"
00117 #define OQPSK500_HSH (0x94)
00118 #define OQPSK500_STR "OQPSK500"
00119 #define OQPSK1000_HSH (0x34)
00120 #define OQPSK1000_STR "OQPSK1000"
00121 #define OQPSK2000_HSH (0x54)
00122 #define OQPSK2000_STR "OQPSK2000"
00123
00124 #define RATE_NONE_HSH (0xFF)
00125
00126
00127
00128 #define TRX_NEXT_CHANNEL(x) ((channel_t)(x+1) > TRX_MAX_CHANNEL ? TRX_MAX_CHANNEL : x+1)
00129 #define TRX_PREV_CHANNEL(x) ((channel_t)(x-1) < TRX_MIN_CHANNEL ? TRX_MIN_CHANNEL : x-1)
00130 #define TRX_NEXT_CHANNEL_WRAP(x) ((channel_t)(x+1) > TRX_MAX_CHANNEL ? TRX_MIN_CHANNEL : x+1 )
00131 #define TRX_PREV_CHANNEL_WRAP(x) ((channel_t)(x-1) < TRX_MIN_CHANNEL ? TRX_MAX_CHANNEL : x-1 )
00132
00133
00134 #if defined (SR_MASK_AMI) || defined(DOXYGEN)
00135
00136 # define TRX_IRQ_AMI_EI() trx_bit_write(SR_MASK_AMI, 1);
00137
00138 # define TRX_IRQ_AMI_DI() trx_bit_write(SR_MASK_AMI, 0);
00139 #endif
00140
00141 #if defined (SR_MASK_BAT_LOW) || defined(DOXYGEN)
00142
00143 # define TRX_IRQ_BAT_LOW_EI() trx_bit_write(SR_MASK_BAT_LOW, 1);
00144
00145 # define TRX_IRQ_BAT_LOW_DI() trx_bit_write(SR_MASK_BAT_LOW, 0);
00146 #endif
00147
00148 #if defined (SR_MASK_CCA_ED_READY) || defined(DOXYGEN)
00149
00150 # define TRX_IRQ_CCA_ED_READY_EI() trx_bit_write(SR_MASK_CCA_ED_READY, 1);
00151
00152 # define TRX_IRQ_CCA_ED_READY_DI() trx_bit_write(SR_MASK_CCA_ED_READY, 0);
00153 #endif
00154
00155 #if defined (SR_MASK_PLL_UNLOCK) || defined(DOXYGEN)
00156
00157 # define TRX_IRQ_PLL_UNLOCK_EI() trx_bit_write(SR_MASK_PLL_UNLOCK, 1);
00158
00159 # define TRX_IRQ_PLL_UNLOCK_DI() trx_bit_write(SR_MASK_PLL_UNLOCK, 0);
00160 #endif
00161
00162 #if defined (SR_MASK_RX_START) || defined(DOXYGEN)
00163
00164 # define TRX_IRQ_RX_START_EI() trx_bit_write(SR_MASK_RX_START, 1);
00165
00166 # define TRX_IRQ_RX_START_DI() trx_bit_write(SR_MASK_RX_START, 0);
00167 #endif
00168
00169 #if defined (SR_MASK_TRX_IRQ_END) || defined(DOXYGEN)
00170
00171 # define TRX_IRQ_TRX_IRQ_END_EI() trx_bit_write(SR_MASK_TRX_IRQ_END, 1);
00172
00173 # define TRX_IRQ_TRX_IRQ_END_DI() trx_bit_write(SR_MASK_TRX_IRQ_END, 0);
00174 #endif
00175
00176 #if defined (SR_MASK_TRX_IRQ_START) || defined(DOXYGEN)
00177
00178 # define TRX_IRQ_TRX_IRQ_START_EI() trx_bit_write(SR_MASK_TRX_IRQ_START, 1);
00179
00180 # define TRX_IRQ_TRX_IRQ_START_DI() trx_bit_write(SR_MASK_TRX_IRQ_START, 0);
00181 #endif
00182
00183 #if defined (SR_MASK_UR) || defined(DOXYGEN)
00184
00185 # define TRX_IRQ_UR_EI() trx_bit_write(SR_MASK_UR, 1);
00186
00187 # define TRX_IRQ_UR_DI() trx_bit_write(SR_MASK_UR, 0);
00188 #endif
00189
00190
00191 #ifdef __cplusplus
00192 extern "C" {
00193 #endif
00194
00195 #if !defined(TRX_IF_RFA1)
00196
00205 void trx_io_init (uint8_t spirate);
00206 #else
00207 #define trx_io_init(dummy) do { } while (0)
00208 #endif
00209
00210
00213 void trx_set_irq_handler(trx_irq_handler_t irqhandler);
00214
00222 void trx_reg_write(trx_regaddr_t addr, trx_regval_t val);
00223
00232 uint8_t trx_reg_read(trx_regaddr_t addr);
00233
00234
00235
00251 trx_regval_t trx_bit_read(trx_regaddr_t addr, trx_regval_t mask, uint8_t pos);
00252
00253
00270 void trx_bit_write(trx_regaddr_t addr, trx_regval_t mask, uint8_t pos, trx_regval_t value);
00271
00282 void trx_frame_write(uint8_t length, uint8_t *data);
00283
00295 uint8_t trx_frame_read(uint8_t *data, uint8_t datasz, uint8_t *lqi);
00296
00297
00313 uint8_t trx_frame_read_crc(uint8_t *data, uint8_t datasz, bool *crc_ok);
00314
00315
00333 uint8_t trx_frame_read_data_crc(uint8_t *data, uint8_t datasz, uint8_t *lqi, bool *crc_ok);
00334
00342 uint8_t trx_frame_get_length(void);
00343
00354 void trx_sram_write(trx_ramaddr_t addr, uint8_t length, uint8_t *data);
00355
00364 void trx_sram_read(trx_ramaddr_t addr, uint8_t length, uint8_t *data);
00365
00375 void trx_parms_get(trx_param_t *p);
00376
00389 uint8_t trx_parms_set(trx_param_t *p);
00390
00402 uint8_t trx_set_datarate(uint8_t rate_type);
00403
00408 uint8_t trx_get_datarate(void);
00409
00414 uint8_t trx_get_number_datarates(void);
00415
00426 void * trx_get_datarate_str_p(uint8_t idx);
00427
00434 void * trx_decode_datarate_p(uint8_t rhash);
00435
00445 uint8_t trx_get_datarate_str(uint8_t idx, char * rstr, uint8_t nlen);
00446
00456 uint8_t trx_decode_datarate(uint8_t rhash, char * rstr, uint8_t nlen);
00457
00458
00459
00460
00461
00462
00463
00467 static inline void trx_init(void)
00468 {
00469 uint8_t val;
00470
00471
00472 TRX_RESET_LOW();
00473 TRX_SLPTR_LOW();
00474 DELAY_US(TRX_RESET_TIME_US);
00475 TRX_RESET_HIGH();
00476
00477
00478 trx_reg_write(RG_TRX_STATE, CMD_TRX_OFF);
00479 DELAY_US(TRX_INIT_TIME_US);
00480 val = trx_reg_read(RG_TRX_STATUS);
00481 if (val != TRX_OFF)
00482 {
00483 while(1);
00484 }
00485 }
00486
00496 static inline int trx_identify(void)
00497 {
00498 int ret = 0;
00499
00500 if(RADIO_PART_NUM != trx_reg_read(RG_PART_NUM))
00501 {
00502 ret |= INVALID_PART_NUM;
00503 }
00504
00505 if(RADIO_VERSION_NUM != trx_reg_read(RG_VERSION_NUM))
00506 {
00507 ret |= INVALID_REV_NUM;
00508 }
00509 return ret;
00510 }
00511
00515 static inline void trx_set_panid(uint16_t panid)
00516 {
00517 trx_reg_write(RG_PAN_ID_0,(panid&0xff));
00518 trx_reg_write(RG_PAN_ID_1,(panid>>8));
00519 }
00520
00525 static inline void trx_set_shortaddr(uint16_t shortaddr)
00526 {
00527 trx_reg_write(RG_SHORT_ADDR_0,(shortaddr&0xff));
00528 trx_reg_write(RG_SHORT_ADDR_1,(shortaddr>>8));
00529 }
00530
00531
00532
00533 #ifdef __cplusplus
00534 }
00535 #endif
00536
00540 #endif